1. Field of the Invention
This invention relates to computer systems and more particularly to interrupt controllers and power management within computer systems.
2. Description of the Related Art
An on-going developmental goal of manufacturers has been to reduce the power consumption of computer systems. Reducing power consumption typically reduces heat generation of the system, thereby increasing reliability and decreasing cost. In addition, power reduction has been particularly important in maximizing the operating life of battery-powered portable computer systems.
Various techniques have been devised for reducing the power consumption of computer systems. These techniques include increasing the integration of circuitry and incorporation of improved circuitry and power management units (PMU's). One specific power reduction technique involves the capability of stopping clock signals that drive inactive circuit portions. A system employing such a technique typically includes a power management unit that detects or predicts inactive circuit portions and accordingly stops the clock signals associated with the inactive circuit portions. By turning off "unused" clock signals that drive inactive circuit portions, overall power consumption of the system is decreased. A similar technique involves the capability of reducing the frequency of clock signals that drive circuit portions during operating modes which are not time critical.
The power management techniques of stopping and/or reducing the frequency of selected clock signals as described above are frequently employed within interrupt driven systems. In an interrupt driven system, peripheral and I/O devices such as keyboards, displays, timers, sensors and other components execute certain tasks independently of the central resource or microprocessor, but require communication with the microprocessor at irregular, random, and therefore asynchronous intervals. In such systems, a particular peripheral or I/O device generates an interrupt signal which is passed on to the microprocessor via a dedicated interrupt line or channel to request that the microprocessor interrupt its processing and service the particular peripheral or I/O device. Upon detecting an active interrupt request, the microprocessor transfers control to service the particular request.
A microprocessor typically services many peripheral devices over a single input-output channel which can only be utilized by one peripheral at a time. Consequently, a priority is assigned to the various peripheral devices to discriminate between concurrent interrupt requests to service the most urgent before the others. Conventional systems have dealt with the problem of multiple interrupt sources by providing an interface circuit between the microprocessor and the peripherals to centrally sort, prioritize and control the interrupt sequencing. One such circuit is the 8259A series programmable interrupt controller manufactured by Advanced Micro Devices, Inc. and described in the publication "MOS Microprocessors and Peripherals"; pp. 3-371 through 3-388 (Advanced Micro Devices, Inc. 1987). This publication is incorporated herein by reference in its entirety.
Most interrupt controllers handle interrupt requests from eight or more peripherals or I/O devices. Each interrupt source is provided an interrupt service routine at a specified vectoral address for servicing the interrupt request. Each interrupt source has its own interrupt request line, and programmable. controllers such as the 8259A allow for identification and prioritization of the various sources upon system initialization. In typical operation, the interrupt controller recognizes interrupt requests and passes the highest priority request to the microprocessor, while holding lower priority requests until the processor has completed servicing the interrupt in progress.
When a power management unit within an interrupt driven system has stopped or reduced the frequency of the clock signals associated with, for example, the microprocessor, the memory subsystems, and/or other peripherals, the power management unit typically monitors the interrupt request lines to detect subsequent system activity. If an interrupt request signal is detected, the power management unit re-starts or increases the frequency of the clock signals of the microprocessor and other peripheral components to thereby allow prompt execution of the interrupt service routine. Since the power management unit is typically unaware of when a particular interrupt service routine has completed, the power management unit re-stops or reduces the frequency of the clock signals after an estimated period of time has elapsed.
An event that involves special consideration with respect to power management is the occurrence of a timer tick interrupt. A timer tick interrupt, also referred to as the system "heartbeat", is an interrupt generated by a timing unit for maintaining time keeping functions within the computer system. The timer tick interrupt occurs 18.2 times per second within a typical computer system, regardless of other system activity. When the timer tick interrupt is received by the microprocessor, a timer tick service routine is executed which, for example, updates system clocks, etc. Since (contrary to the occurrence of most other interrupt request signals), the occurrence of a timer tick interrupt is not correlated with a probability of further system activity, the power management unit usually treats a timer tick interrupt specially by "waking up" the computer system (that is, by restarting selected clock signals and/or raising the frequency of selected clock signals) for 120 microseconds. The power management unit subsequently causes the computer system to return to a "dozing" state during which the selected clock signals are again stopped and/or slowed. Unfortunately this estimated wake-up time period is often inaccurate and thus leads to wasted system power.